An ordinary memory is constructed such that it has input terminals the number of which corresponds to the number of bits of a data to be written therein, output terminals the number of which corresponds to the number of bits of a data to be read out therefrom, and address terminals the number of which corresponds to the number of bits of an address signal, wherein parallel data and a parallel address signal are supplied to the plurality of input terminals and the plurality of address terminals respectively to store the parallel data in the memory and a parallel address signal is supplied to the address terminals to read the stored data from the plurality of the output terminals as parallel data. That is, the ordinary memory is a parallel input/parallel output type memory. Further, the address terminals are generally used in common for write and read operations of parallel data.
In a memory testing apparatus, parallel data read out of a memory under test are logically compared with parallel expected value data in logical comparator means. Parallel failure data resulted from the logical comparisons are supplied to a failure analysis memory and positions of failure memory cells of the tested memory are stored in memory cells of the failure analysis memory at cell positions thereof having their addresses corresponding to those of the cell positions of the tested memory. The information of the positions of failure memory cells and the number of failure memory cells stored in the failure analysis memory are utilized in performing a failure analysis of the tested memory and the like.
In recent years, there has been developed a memory having the least terminals possible. The memory of this type has therein a shift register train (a series of shift registers) called "SCAN chain" in this technical field. Such memory is arranged that an input terminal of the first stage shift register and an output terminal of the last stage shift register of the shift register train are led out therefrom to the outside, that an address signal and data to be written are inputted from this input terminal to the shift register train as a serial signal and are sequentially fed into input side shift registers of the shift register train, that the input data serially supplied to the shift register train are taken out from the input side shift registers in parallel and are stored in the memory for each address, that the data stored in the memory are read out in parallel thereof and are taken in output side shift registers of the shift register train as a parallel signal, and that the parallel data stored in output side shift registers are taken out from the output terminal of the last stage shift register of the shift register train as a serial signal by sequentially shifting the shift register train.
In such a way, by constructing a memory as a serial input/serial output type memory structure, there is obtained an advantage that the number of terminals of the memory can be reduced to a minimum.
FIG. 4 illustrates the internal structure of an example of the serial input/serial output type memory. In the drawing the serial input/serial output type memory which is to be a memory under test is denoted as a whole by a reference numeral 12. This memory under test 12 includes a built-in memory cell array 12A and a shift register train called SCAN chain. There are provided, in this example, four input terminals T0-T3 and four output terminals T4-T7 in the memory cell array 12A. Therefore, the shift register train is correspondingly constructed such that four shift registers R0-R3 disposed in the input side thereof and four shift registers R4-R7 disposed in the output side thereof are connected in series, an input terminal of the first stage shift register R0 is led out therefrom as an external input terminal IN, and an output terminal of the last stage shift register R7 is led out therefrom as an external output terminal OUT.
Serial data inputted from the external input terminal IN into the shift register train are fed into the four shift registers R0, R1, R2 and R3 in the input side connected in series with one another and are temporarily stored therein. After then, the temporarily stored serial data are written in the memory cell array 12A as parallel data from the shift registers R0-R3 via the four input terminals T0-T3 by a write signal and are stored therein.
Output data read out, in parallel, from the four output terminals T4-T7 of the memory cell array 12A by a read signal are temporarily stored in the corresponding shift registers R4-R7 in the output side. The read out data stored in the shift registers R4-R7 are converted to serial data by sequentially shifting the shift registers R4-R7, which serial data are outputted from the external output terminal OUT as a serial signal.
In such a manner, in case of a serial input/serial output type memory, it has only one input terminal and one output terminal, and hence the number of terminals can significantly be reduced.
FIG. 5 shows the general circuit configuration of a typical conventional memory testing apparatus which is configured such that it is capable of testing either of a serial input/serial output type memory and a parallel input/parallel output type memory. This memory testing apparatus includes a pattern generator 11 for generating a predetermined test pattern signal, an address pattern signal, an expected value data signal and the like, a logical comparator 13 for logically comparing an output data read out from a memory under test 10 with an expected value data supplied from the pattern generator 11, a failure multiplexer 14, a failure analysis memory 15, and an address selector 16.
The pattern generator 11 has a group of output terminals 11A for outputting an address pattern signal, a group of output terminals 11B for outputting a test pattern signal and a group of output terminals 11C for outputting an expected value data, and outputs, when the memory under test 10 is a parallel input/parallel output type memory, parallel address pattern signals, parallel test pattern signals and parallel expected value data signals from those output terminal groups 11A, 11B and 11C, respectively.
Output data read out from the memory under test 10 are inputted to one group of input terminals 13A of the logical comparator 13. Expected value data are supplied from the pattern generator 11 to the other group of input terminals 13B of the logical comparator 13 where the output data from the memory under test 10 are logically compared with the expected value data from the pattern generator.
The logical comparator 13 outputs a pass signal (usually a logical "0" signal) indicating that the tested memory cell is good or non-defective when the both data coincide with each other, and outputs a failure signal (usually a logical "1" signal), as a failure data, indicating that the tested memory cell is defective or failure when the both data do not coincide with each other. The failure data is sent to a failure multiplexer 14, and the failure data from one of the terminals of the memory under test 10 selected by the failure multiplexer 14 is inputted to the failure analysis memory 15 and is stored in a memory cell of the failure analysis memory 15 having the same address as that of the failure memory cell of the memory under test 10. The failure multiplexer 14 selects one of the terminals of the memory under test 10 the failure data from which is taken in the failure analysis memory 15 for each bit of the failure analysis memory 15. In addition, an address pattern signal outputted from the pattern generator 11 is supplied to the memory under test 10 and, at the same time, is also supplied to the failure analysis memory 15 via an address selector 16. Therefore, the failure data can be stored in a memory cell of the failure analysis memory 15 having the same address as that of the failure memory cell of the memory under test 10.
Now, functions of the address selector 16 and the failure multiplexer 14 will be described.
A memory testing apparatus needs to be able to test memories having various storage capacities. Therefore, the storage capacity of a memory under test 10 is not fixed and hence, the memory testing apparatus tests various memories having their storage capacities from small to large storage capacities. On the other hand, the storage capacity of the failure analysis memory 15 is determined depending upon the machine type of a memory testing apparatus and is fixed. Therefore, a case may occur that the storage capacity of the failure analysis memory 15 will be smaller than that of the memory under test 10.
Even in such case, in order to make it possible that the test results can be stored in the failure analysis memory 15, the memory testing apparatus is arranged such that the output terminals of the memory under test 10 the test results from which are to be stored in the failure analysis memory 15 can be selected by the failure multiplexer 14. That is, the memory testing apparatus is arranged such that only the logical comparison results from the output terminals of the memory under test 10 specified by the failure multiplexer 14 can be inputted to the failure analysis memory 15. Accordingly, in order to match the range of the terminals of the memory under test 10 to be selected with the range of addresses, the address selector 16 also selects the bits of the address signal, thereby to specify the address range.
The above explanation is with respect to the operations in testing an ordinary parallel input/parallel output type memory. Next, operations in testing a serial input/serial output type memory will be described.
In case of testing a serial input/serial output type memory, the pattern generator 11 outputs a serial address pattern signal, a serial test pattern signal and a serial expected value data signal from one output terminal of the output terminal group 11A, from one output terminal of the output terminal group 11B and from one output terminal of the output terminal group 11C, respectively.
The logical comparator 13 logically compares serial data outputted from the memory under test 10 with serial expected value data and the logical comparison results (failure data) are inputted to the failure analysis memory 15 via the failure multiplexer 14. Therefore, the failure data form a serial signal. This serial failure data is supplied to one input terminal of the failure analysis memory 15 as data from one terminal of the memory under test selected by the failure multiplexer 14.
A serial address pattern signal outputted from one output terminal of the address signal output terminal group 11A of the pattern generator 11 is converted, if necessary, in the address selector 16 from a serial signal to parallel signals. The parallel address signals are supplied to address input terminals of the failure analysis memory 15 to access an address of the failure analysis memory 15.
As mentioned above, in case of testing a serial input/serial output type memory by use of a conventional memory testing apparatus, a serial failure data is directly supplied to the failure analysis memory 15 in the form of a serial signal and this serial failure data is written in memory cells each having one bit one data for one memory cell at respective addresses of the failure analysis memory 15. Therefore, there occurs a disadvantage that a bit position where a failure has occurred (a cell position where a failure has occurred in memory cells) of the tested memory cannot be specified and hence cannot be stored in the failure analysis memory 15 in the state that the failure bit position has been specified.
That is, since a serial failure data constituted by a plurality of bits aligned in the direction of time series is sequentially stored in memory cells, each having one bit, of the failure analysis memory, there occurs an disadvantage that even if a logical "1" indicating a failure is written in one memory cell of the failure analysis memory 15, it is impossible to specify in which bit of the memory the failure indicated by this logical "1" has been occurred. As a result, there is a drawback that it takes a long time to test a serial input/serial output type memory and to specify a failure position of the memory.